A composite video signal is the sum of a luminance (brightness) signal and a chrominance (color) signal. These signals may be referred to as luma and chroma signals, respectively. The frequency ranges of the luma and chroma signals are designed to overlap. In video processing, the luma and chroma signal components are added together in order to generate a composite video signal. The luma and chroma video elements are integrated and broadcasted as a single composite video stream. Once the broadcasted composite signal is received, the luma and chroma signal components may be separated in order for the video signal to be processed and displayed. A comb filter may be utilized for separating the chroma and luma video signal components. For example, a television may be adapted to receive a composite video input and utilize an integrated comb filter to separate the chroma and luma video signal components. However, before the television can display the received video signal, the chroma and luma video components have to be separated.
In a flow control based system, for example, a video processing system, a set of processes may be deadlocked if each process in a set is waiting for an event that only another process in the set may cause. As all the processes are waiting, none of them may ever cause any of the events that may wake up any of the other members of the set, and all the processes may continue to wait forever. Each member of the set of deadlocked processes may be waiting for a resource that is owned by a deadlocked process. As a result, none of the processes may be able to run or release any resources, and none of them may be awakened.
In the flow control based data path design, each block may receive and process data asynchronously. When a programming error occurs, it may cause a pipeline to stall, for example, a deadlock situation for a distributed and merge design. The system may not be able to self-recover from a deadlock situation, even when the programming error has been rectified and may be resolved only by a manual reset.
FIG. 1 is a block diagram of a conventional system that utilizes a distribute and merge data processing system. Referring to FIG. 1, the system 100 comprises a distribute control block 102, luma filter 104, chroma filter 106 and merge control block 108. The distribute control block 102 may receive data from similar distribute and merge data processing systems and distribute data between two or more data paths, for example, path 1 and path 2. The luma filter 104 may be a notch and bandpass filter, for example, and may be adapted to allow luma data through and block chroma data. The chroma filter 106 may be a comb filter, for example, and may be adapted to separate chroma data from luma data in the frequency domain. The merge control block 108 may be adapted to receive data from path 1 and path 2, and merge this data from two or more data paths, for example, path 1 and path 2.
In operation, when another similar system intends to transmit data to distribute control block 102, it may send a i_ready signal to distribute control block 102. When distribute control block 102 is ready to accept data it may send an acknowledge signal o_accept and may begin to accept data. When distribute control block 102 has data ready to be transmitted to the luma filter 104, it may send a ready1.p1 signal to the luma filter 104 and when the luma filter 104 is ready to accept data it may respond by sending an accept1.p1 signal back to distribute control block 102 and data may begin to flow from distribute control block 102 to the luma filter 104. The luma filter 104 may continue to receive and process data until it reaches its capacity. When the luma filter 104 intends to transmit data downstream to the merge control block 108, it may send a ready2.p1 signal to the merge control block 108. When the merge control block 108 is ready to accept data it may send an acknowledge accept2.p1 signal back to the luma filter 104 and data may begin to flow from the luma filter 104 to the merge control block 108. When the merge control block 108 intends to transmit data to another similar system it may send an o_ready signal and begin transmitting data when it receives an i_accept signal from the other system.
When the distribute control block 102 has data ready to be transmitted to the chroma filter 106, it may send a ready1.p2 signal to the chroma filter 106 and when the chroma filter 106 is ready to accept data it may respond by sending an accept1.p2 signal back to distribute control block 102 and data may begin to flow from distribute control block 102 to chroma filter 106. The chroma filter 106 may continue to receive and process data until it reaches its capacity. When the chroma filter 106 intends to transmit data downstream to the merge control block 108, it may send a ready2.p2 signal to the merge control block 108. When the merge control block 108 is ready to accept data it may send an acknowledge signal accept2.p2 back to the chroma filter 106 and data may begin to flow from the chroma filter 106 to the merge control block 108.
A programming error may cause a deadlock situation to arise in a distribute and merge data processing system, wherein one of the data paths may be full of data, while the other data path may be empty. The deadlock situation may not be resolved by correcting the programming error, and the only way the distribute and merge data processing system may recover from the deadlock situation is by a manual reset of hardware, which may cause a loss of valuable information.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.